1. Field of the Invention
This invention relates in general to semiconductor memory devices, and more particularly to a structure of a dynamic random access memory (DRAM) cell substantially composed of a transfer transistor and a charge storage capacitor.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a memory cell for a DRAM device. As shown in the drawing, a DRAM cell is substantially composed of a transfer transistor T and a charge storage capacitor C. A source of the transfer transistor T is connected to a corresponding bit line BL, and a drain thereof is connected to a storage electrode 6 of the charge storage capacitor C. A gate of the transfer transistor T is connected to a corresponding word line WL. An opposing electrode 8 of the capacitor C is connected to a constant power source. A dielectric film 7 is provided between the storage electrode 6 and the opposing electrode 8.
In the DRAM manufacturing process, a two-dimensional capacitor called a planar type capacitor is mainly used for a conventional DRAM having a storage capacity less than 1M (mega=million) bits. In the case of a DRAM having a memory cell using a planar type capacitor, electric charges are stored on the main surface of a semiconductor substrate, so that the main surface is required to have a large area. This type of a memory cell is therefore not suited to a DRAM having a high degree of integration. For a high integration DRAM such as a DRAM with more than 4M bits of memory, a three-dimensional capacitor, called a stacked-type or a trench-type capacitor, has been introduced.
With the stacked-type or trench-type capacitors, it has been made possible to obtain a larger memory in a similar volume. However, to realize a semiconductor device of an even higher degree of integration, such as a very-large-scale integration (VLSI) circuit having a capacity of 64M bits, a capacitor of such a simple three-dimensional structure as the conventional stacked-type or trench-type, turns out to be insufficient.
One solution for improving the capacitance of a capacitor is to use the so-called fin-type stacked capacitor, which is proposed in Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", International Electron Devices Meeting, pp. 592-595, December 1988. The fin-type stacked capacitor includes electrodes and dielectric films which extend in a fin shape in a plurality of stacked layers. DRAMs having the fin-type stacked capacitor are also disclosed in U.S. Pat. No. 5,071,783 (Taguchi et al.); U.S. Pat. No. 5,126,810 (Gotou); U.S. Pat. No. 5,196,365 (Gotou); and U.S. Pat. No. 5,206,787 (Fujioka).
Another solution for improving the capacitance of a capacitor is to use the so-called cylindrical-type stacked capacitor, which is proposed in Wakamiya et al., "Novel Stacked Capacitor Cell for 64-Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. The cylindrical-type stacked capacitor includes electrodes and dielectric films which extend in a cylindrical shape to increase the surface areas of the electrodes. A DRAM having the cylindrical-type stacked capacitor also is disclosed in the U.S. Pat. No. 5,077,688 (Kumanoya et al.).
With the trend toward increased integration density, the size of the DRAM cell in a plane (the area it occupies in a plane) must be further reduced. Generally, a reduction in the size of the cell leads to a reduction in charge storage capacity (capacitance). Additionally, as the capacitance is reduced, the likelihood of soft errors arising from the incidence of .alpha.-rays is increased. Therefore, there is still a need in this art to design a new structure of a storage capacitor which can achieve the same capacitance, while occupying a smaller area in a plane, and a suitable method of fabricating the structure.